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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal Bus Transceiver
The MC74VHCT245A is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. It is intended for two-way asynchronous communication between data buses. The direction of data transmission is determined by the level of the DIR input. The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated. All inputs are equipped with protection circuits against static discharge. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings. The VHCT245A input and output (when disabled) structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. * * * * * * * * * * * High Speed: tPD = 4.9ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5V to 5.5V Operating Range Low Noise: VOLP = 1.6V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 304 FETs or 76 Equivalent Gates
MC74VHCT245A
DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-04
DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02
M SUFFIX 20-LEAD SOIC EIAJ PACKAGE CASE 967-01 ORDERING INFORMATION MC74VHCTXXXADW SOIC MC74VHCTXXXADT TSSOP MC74VHCTXXXAM SOIC EIAJ
APPLICATION NOTES 1. Do not force a signal on an I/O pin when it is an active output, damage may occur. 2. All floating (high impedence) input or I/O pins must be fixed by means of pull up or pull down resistors or bus terminator ICs. LOGIC DIAGRAM
A1 A2 A3 A DATA PORT A4 A5 A6 A7 A8 DIR OE 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 B1 B2 B3 B4 B5 B6 B7 B8 B DATA PORT
PIN ASSIGNMENT
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8
FUNCTION TABLE
Control Inputs OE L L H DIR L H X Operation Data Tx from Bus B to Bus A Data Tx from Bus A to Bus B Buses Isolated (High-Z State)
6/97
(c) Motorola, Inc. 1997
1
REV 0
I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII II I I I I I II II I I I I II I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I II I I I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II II I I II II I I I II I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I II I I I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I II I I I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I II I I I I II II I I II II I II II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I I I IIII I I I I IIIIIIIIIIIIIIIIIIIIIII II I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
Tstg Storage Temperature - 65 to + 150 _C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
II I I I I I IIIIIIIIIIIIIIIIIIIIIII I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I I I I I I III IIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MC74VHCT245A
MAXIMUM RATINGS*
VCC VI/O ICC IOK Iout Vin PD IIK Power Dissipation in Still Air, DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current (VOUT < GND; VOUT > VCC)IIIIII 20 mA Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage Outputs in 3-State High or Low State SOIC Packages TSSOP Package - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to + 7.0 - 0.5 to + 7.0 - 20 75 25 500 450 mW mA mA mA V V V
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
MOTOROLA Symbol Symbol S bl VCC IOPD VI/O ICCT VOH tr, tf VOL Vin ICC IOZ VIH TA VIL Iin
Input Rise and Fall Time
Operating Temperature
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Output Leakage Current
Quiescent Supply Current
Maximum Quiescent Supply Current
Maximum 3-State Leakage Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage Vin = VIH or VIL
Minimum High-Level Output Voltage Vin = VIH or VIL
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter P
Parameter
VOUT = 5.5V
Per Input: VIN = 3.4V Other Input: VCC or GND
Vin = VCC or GND
Vin = VIL or VIH Vout = VCC or GND
Vin = 5.5 V or GND
Test C di i T Conditions
Outputs in 3-State High or Low State
VCC =5.0V 0.5V
IOH = - 50A
IOH = - 8mA
IOL = 50A
IOL = 8mA
0 to 5.5
4.5 to 5.5
4.5 to 5.5
VCC V
2
5.5
5.5
5.5
4.5
4.5
4.5
4.5
0
- 40
Min
4.5
0
0 0
0
5.5 VCC
+ 85
Max
3.94
Min
5.5
5.5
4.4
2.0
20
ns/V
Unit
TA = 25C
_C
V
V
V
Typ
0.0
4.5
0.25
0.1
1.35
0.36
Max
0.5
4.0
0.1
0.8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
VHC Data - Advanced CMOS Logic DL203 -- Rev 1 TA = - 40 to 85C 3.80 Min 4.4 2.0
v
2.5
1.0
1.50 40.0 0.44 Max 0.1 0.8
5.0
v
Unit Ui
mA A A A V V V V
A
MC74VHCT245A
II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II II I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol S bl tPLH, tPHL tPZL, tPZH tPLZ, tPHZ Parameter P TA = 25C Typ 4.9 5.4 9.4 9.9 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 Max 8.5 9.5 Test C di i T Conditions Min Max 7.7 8.7 Unit Ui ns ns ns Maximum Propagation Delay A to B or B to A Output Enable Time OE to A or B VCC = 5.0 0.5V VCC = 5.0 0.5V RL = 1k VCC = 5.0 0.5V RL = 1k VCC = 5.0 0.5V (Note NO TAG) CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF 13.8 14.8 15.4 1.0 10 15.0 16.0 16.5 1.0 10 Output Disable Time OE to A or B 10.1 tOSLH, tOSHL Cin Output to Output Skew pF pF pF Maximum Input Capacitance 4 Cout Maximum Three-State Output Capacitance (Output in High-Impedance State) 13 Typical @ 25C, VCC = 5.0V 16 CPD Power Dissipation C P Di i i Capacitance (N i (Note NO TAG) 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. pF F 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol S bl VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter P Typ 1.2 -1.2 Max 1.6 -1.6 2.0 0.8 Unit Ui V V V V
SWITCHING WAVEFORMS
3V DIR 1.5V GND 3V 3V A or B tPLH B or A 1.5V 1.5V GND tPHL VOH VOL A or B A or B OE 1.5V tPZL 1.5V tPZH 1.5V tPHZ tPLZ 1.5V GND HIGH IMPEDANCE VOL +0.3V VOH -0.3V HIGH IMPEDANCE
Figure 1.
Figure 2.
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
3
MOTOROLA
MC74VHCT245A
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 3. EXPANDED LOGIC DIAGRAM
Figure 4.
A1
2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B8 B7 B6 B5 B4 B3 B2 B1
A2
A3
A4
A5
A6
A7
A8
DIR
1
OE
19
MOTOROLA
4
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHCT245A
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
-A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
2X
L/2
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
5
IIII IIII IIII
SECTION N-N M DETAIL E
20
11
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MOTOROLA
MC74VHCT245A
OUTLINE DIMENSIONS
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MOTOROLA
6
MC74VHCT245A/D VHC Data - Advanced CMOS Logic DL203 -- Rev 1

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